1. Field of the Invention
The present invention relates generally to Short Channel Effects (SCEs) within Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). More particularly, the present invention relates to methods for control of Hot Carrier Effect (HCE) Short Channel Effects (SCEs) within MOSFETs.
2. Description of the Related Art
As semiconductor technology continues to advance, and the dimensions of integrated circuit device and conductor element features within integrated circuits continues to decrease, several novel effects arise within integrated circuits. In particular, within advanced integrated circuits within which there are formed Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), there arises a general category of novel effects known as Short Channel Effects (SCEs). SCEs typically derive from: (1) the narrowing of gate electrode dimensions within advanced MOSFETs, and/or (2) the thinning of gate oxide layers which reside beneath those narrow gate electrodes within advanced MOSFETs.
A common and detrimental Short Channel Effect (SCE) within MOSFETs is the Hot Carrier Effect (HCE). The HCE derives from increased electrical fields within advanced MOSFETs, which increased electrical fields result from decreasing gate oxide thickness within those MOSFETs while maintaining constant MOSFET operating voltages. The increased electrical fields accelerate charge carriers from the semiconductor substrate upon which the MOSFET is formed into the gate oxide layer of the MOSFET, where the accelerated charge carriers are captured by free electron states within the gate oxide layer.
Several methods have conventionally been employed in the art to limit Hot Carrier Effects (HCEs) within advanced MOSFETs. Included among these methods are: (1) reductions in MOSFET operating voltages, (2) increases in MOSFET gate oxide hardness to hot carrier injection, such as obtained by incorporating fluorine or nitrogen into the gate oxide, and (3) incorporation of Lightly Doped Drain (LDD) low dose ion implant structures within the semiconductor substrates beneath MOSFET gate electrode edges. Each of these methods will reduce the electric field gradient from the channel region of a MOSFET to the highly doped source/drain electrodes which adjoin the channel region of the MOSFET. Of these methods, the LDD structure has gained the most wide acceptance, although the LDD structure requires additional masking and ion implantation steps while typically yielding a MOSFET structure which still exhibits residual, although reduced, HCEs.
Non-traditional methods for control of HCEs within MOSFETs have also been disclosed in the art. For example, Rodder, in U.S. Pat. No. 5,108,935 discloses a method for reducing HCEs within MOSFETs by increasing the scattering rate of hot carriers within semiconductor substrates. The increased scattering rate is achieved through incorporating non-conventional dopants into channel regions of MOSFETs.
Although not specifically related to HCEs, methods are also known in the art whereby undesirable movement of other mobile species within MOSFET structures may also be inhibited. For example, methods by which migration of mobile fluorine species within polysilicon gate electrodes of MOSFETs may be inhibited are disclosed by Anjum, et al., in U.S. Pat. No. 5,393,676. Disclosed is a method whereby argon atoms are implanted to form a barrier within a polysilicon gate electrode, beyond which barrier migration of mobile fluorine species is inhibited.
Desirable in the art are additional novel methods whereby SCEs such as the HCE within MOSFETs may be controlled. Particularly desirable are methods which provide for exceedingly high immunity to HCEs within a MOSFET while simultaneously avoiding the masking and ion implantation process steps associated with forming a conventional LDD structure within the MOSFET.